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Wednesday, March 25, 2009

DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings

DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings
Aayush Gupta Youngjae Kim Bhuvan Urgaonkar
Department of Computer Science and Engineering
The Pennsylvania State University, University Park, PA 16802, USA
{axg354, youkim, bhuvan}@cse.psu.edu

This paper argues that page level FTL has better performance than block level or hybrid type FTL, and propose cache algorithm to get over the disadvantage of page level FTL. Since page level FTL requires much of memory to store mapping table, the paper proposed cache algorithm to reduce required memory.

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